;
macro notes
nb2a.src
DB20 change meaning of loforw and lorev
D901 installed on DE0
endm
.include cpu16a.h
Fchop .sys 480 ; desired chop frequency
CPL .sys 8 ; cycles per loop iteration
Mhz .sys 10**6
Fxtal .sys 50*Mhz
Fclk .sys Fxtal/8 ; clock divider
maxpwm .equ Fclk/Fchop/CPL ; 1627
stepsize .sys 42
; i/o mappe
status .equ 0x400 ; r
rxdata .equ 0x401
version .equ 0x402
pbport .equ 0x403
; pbport bits
; 13 forw
; 11 apply
; 3 test mode
; 2 use radio (only with nbrf wrapper)
; 1 hard reset (hardware)
; 0 use PBs instead of direct inputs
ind .equ 0x40b ; w
hex0 .equ 0x40c
hex1 .equ 0x40d
gled .equ 0x40e
rled .equ 0x40f
ctrl .equ 0x420 ; echo 400
txdata .equ 0x421 ; echo 401
maxpb .sys 50
;;maxpb .sys 2
bp .sys 0x30
cntr .equ bp+0
pwm .equ bp+1
inctmr .equ bp+2
led .equ bp+3
ledbk .equ bp+4
dro .equ bp+5
; .equ bp+6
indbk .equ bp+7
ivcnt .equ bp+8
chg .equ bp+9
bp .sys chg+1
; Ctrl bits
dfield .sys bit.0 ; B6
lorev .sys bit.1 ; B8
hiforw .sys bit.2 ; B2
loforw .sys bit.3 ; B10
hirev .sys bit.4 ; B4
; Status bits
release .sys bit.0 ; C B21
apply .sys bit.1 ; Z B23
rear .sys bit.2 ; V B25
front .sys bit.3 ; N B27
overcur .sys bit.4 ; P B35
underv .sys bit.5 ; O B31
short .sys bit.6 B37
; bit.7 B33 unused
rxrdy .sys bit.8
txbusy .sys bit.9
; IND bits
red .sys bit.0 ; hi current
orn .sys bit.1 ; dynamic
yel .sys bit.2 ; low battery
grn .sys bit.3 ; forward
blu .sys bit.4 ; reverse
vio .sys bit.5 ; hi range
blinktime .sys 200
;;blinktime .sys 20
.org 0x1000
startup
mov r0,#255 ; clear low 256 RAM
clr r1
rx00
mov @r0,r1
dec r0
jp rx00
mov r2,#-1
mov r1,#revision
jsr wtdro
;; mov r0,#2
;; mov status,r0
;; clr r0
;; mov pbport,r0
mcall tests
jt max_d
; idle forward
idle_f
mov r2,#grn
mov r1,#0xF000
jsr wtdro
if00
clr r0
mov pwm,r0
mov r1,#hiforw
mov r2,r1
jsr mon2
jv idle_f ; rear
jn norm_f ; front
jz dyn_f ; apply
jt if00
idle_r
mov r2,#blu
mov r1,#0xA000
jsr wtdro
ir00
clr r0
mov pwm,r0
mov r1,#hirev
mov r2,r1
jsr mon2
jv norm_r ; rear
jn idle_r ; front
jz dyn_r ; apply
jt ir00
norm_f
mov r2,#grn
mov r1,#0xF000
jsr wtdro
lf00
mov r1,#(hiforw)
mov r2,#(hiforw+loforw)
jsr mon2
jpo dec_f ; hi-i
jo dec_f ; lo-v
jcs idle_f ; deapply
jz idle_f ; apply
jv dec_f ; rear
jn inc_f ; front
jt lf00
dec_f
jsr decpwm
jz idle_f
jt lf00
inc_f
jsr incpwm
jt lf00
dec_r
jsr decpwm
jz idle_r
jt lr00
inc_r
jsr incpwm
jt lr00
norm_r
mov r2,#blu
mov r1,#0xA000
jsr wtdro
lr00
mov r1,#(hirev)
mov r2,#(hirev+lorev)
jsr mon2
jpo dec_r ; hi-i
jo dec_r ; lo-v
jcs idle_r ; deapply
jz idle_r ; apply
jv inc_r ; rear
jn dec_r ; front
jt lr00
dyn_f
mov r2,#grn+orn
mov r1,#0xD000
jsr wtdro
df00
mov r1,#(dfield+loforw)
mov r2,#(dfield+loforw+lorev)
jsr mon2
jpo dec_df ; hi-i
jcs dec_df ; deapply
jz inc_df ; apply
jv idle_f ; rear
jn idle_f ; front
jt df00
dec_df
jsr decpwm
jt df00
inc_df
jsr incpwm
jcs df00
max_d
mov r2,#orn
mov r1,#0xD999
jsr wtdro
md00
mov r1,#(dfield+loforw+lorev)
mov r2,r1
jsr mon2
jcs md00 ; deapply
jz md00 ; apply
jv idle_r ; rear
jn idle_f ; front
jt md00
dec_dr
jsr decpwm
jt dr00
inc_dr
jsr incpwm
jcc max_d
jt dr00
dyn_r
mov r2,#blu+orn
mov r1,#0xB000
jsr wtdro
dr00
mov r1,#(dfield+lorev)
mov r2,#(dfield+lorev+loforw)
jsr mon2
jpo dec_dr ; hi-i
jcs dec_dr ; deapply
jz inc_dr ; apply
jv idle_r ; rear
jn idle_r ; front
jt dr00
incpwm
mov r1,#stepsize
jt inc01
decpwm
mov r1,#-stepsize
inc01
mov r0,inctmr
inc r0
mov inctmr,r0
cmp r0,#maxpb
jn inc99
clr r0
mov inctmr,r0
add r1,r1,pwm
jp inc02
clr r1
inc02
cmp r1,#maxpwm
jn inc03
mov r1,#maxpwm
inc03
mov pwm,r1
mulu r0,r1,#((999/maxpwm)<<16)
; r1 < 0 to 9999 binary
; r5 > BCD output
; (uses r0:r6)
mulu r0,r1,#(2**28/10000+1)
mov r6,#5 ; digits
px10
mov r4,r1
shl r4,r4,#4 ; roll digit into output
and r1,r1,#0xfff ; remove digit from remainder
mulu r2,r1,#10 ; multiply remainder by 10
mulu r0,r0,#10
add r1,r1,r2
dec r6,r6
jnz px10
mov r0,dro
and r0,r0,#0xf000
or r1,r5,r0
mov dro,r1
inc99
mov r1,pwm
cmp r1,#maxpwm
bit r1,r1
rtn
macro tloop [inst] ; timing loop (8 cyc)
m$
nop
nop
nop
nop
nop
dec r0
jp m$
endm
yikes
clr r0
mov ctrl,r0
mov r2,#red
or r2,ledbk
mov r1,#0xDEAD
jsr wtdro
;; mov r0,led
;; mov ind,r0
doom
clr r0
mov ctrl,r0
;; jsr debug
jmp doom
;r1 < normal mask
;r2 < pulsed mask
mon2
;; mov dbg.retn,retn
clr r3
mov r0,status
bit r0,#short
jnz yikes
bit r0,#underv
jz *+2
or r3,r3,#yel
or r3,r3,ledbk
mov ledbk,r3
bit r0,#overcur
jz no_over
mov r0,#480
mov ivcnt,r0
no_over
mov r0,ivcnt
test r0
jz no_red
dec r0
mov ivcnt,r0
or r3,r3,#red
no_red
or r3,r3,led
montx
mov ind,r3
mov indbk,r3
mov r0,pwm
bit r0,r0
jz m202
mov ctrl,r2 ; pulse on
;; jsr debug
;; mov r0,pwm
mcall tloop 200
m202
mov ctrl,r1 ; pulse off
;; jsr debug
mov r0,#maxpwm
sub r0,r0,pwm
inc r0
mcall tloop 201
macro opts
mov r1,status
or r1,#0xffc0
mov r2,pbport
bit r2,#bit.0 ; if SW0
jz fin
shr r2,r2,#10
and r2,r2,#15
or r1,r1,#15
andn r1,r1,r2 ; invert and substitute DE1 PBs
fin
endm
mcall opts
mov r2,r1
shl r2,r2,#6
or r2,r2,indbk
mov rled,r2 ; light reds with inputs,leds
mov flags,r1 ; set flags with low 6 status bits
;; jmp @dbg.retn
rtn
mont
;; mov dbg.retn,retn
mov r3,led
jt montx
seg7
; gfedcba
; -------
.dw 0x40<<8 ; 0 0111111
.dw 0x79<<8 ; 1 0000110
.dw 0x24<<8 ; 2 1011011
.dw 0x30<<8 ; 3 1001111
.dw 0x19<<8 ; 4 1100110
.dw 0x12<<8 ; 5 1101101
.dw 0x02<<8 ; 6 1111101
.dw 0x78<<8 ; 7 0000111
.dw 0x00<<8 ; 8 1111111
.dw 0x10<<8 ; 9 1101111
.dw 0x08<<8 ; A 1110111
.dw 0x03<<8 ; B 1111100
.dw 0x46<<8 ; C 0111001
.dw 0x21<<8 ; D 1011110
.dw 0x06<<8 ; E 1111001
.dw 0x0e<<8 ; F 1110001
; U O
; V C F R A D
; - - - - - -
; I O P N V Z C
; r1 < data
; r2 < led on
wtdro
clr r0
mov led,r2
mov dro,r1
rtn
;; .include debug.src
.include tests.src
macro tests
endm
revision .sys 0xD809